1. Field of the Invention
This invention relates to an automatic design technology of a semiconductor integrated circuit described in an HDL (Hardware Description Language) and in particular to a circuit automatic generation apparatus and method unifying a large number of design steps required for creating the top-layer circuit of a semiconductor integrated circuit.
2. Description of the Related Art
Hitherto, a method of automatically generating a logical circuit from a circuit described in the HDL using a logic synthesis tool has been adopted widely as a method of generating a logical circuit of a semiconductor integrated circuit. However, it is a common practice for a designer to manually describe a circuit using a text editor, etc., as a method of describing a circuit in the HDL.
A top down design technique of dividing a semiconductor integrated circuit for each function to form a hierarchical (layered) organization is widely used as a circuit design technique of describing a circuit in the HDL in the related art; a circuit is designed according to the hierarchical (layered) organization technique in function circuit design and in top-layer circuit design of a semiconductor integrated circuit. In the hierarchical (layered) design technique, it is necessary to create a high-layer circuit for connecting input/output signals of a plurality of function circuits formed as low layers.
In recent years, the number of function circuits making up a semiconductor integrated circuit has become enormous with the larger scale and higher function of the semiconductor integrated circuit. To develop such a semiconductor integrated circuit early, the trend of dividing design work among designers for each function circuit appears noticeably. The design process of creating the top-layer circuit of a semiconductor integrated circuit tends to be divided among designers.
To create the top-layer circuit, “input/output information of function circuit,” “circuit information to which function circuit is connected,” and “input/output information of top-layer circuit and circuit information to which top-layer circuit is connected” become necessary.
To create a top-layer circuit closer to the mounting level to which test specifications to conduct shipment inspection of a semiconductor integrated circuit are added, further “test mode signal generation information,” “terminal test specification information,” and “function block circuit information to which test specifications are added” become necessary. These pieces of information are information dependent on the job progress situation of function circuit designers, and are frequently updated.
In a general work dividing system, a design review is conducted for each job in charge and a check is made to ensure that the circuit does not involve any problem and then the job is inherited to the next step. In this method, however, a large number of steps are undergone until completion of a sequence of jobs, and it takes much time until a product high in perfection is obtained in the job in which the correction frequency is high.
The design method of creating the top-layer circuit of a semiconductor integrated circuit is conducted, for example, in the order of “function circuit creation,” “test mode signal generation circuit creation,” “terminal test circuit creation,” “test circuit installation in function circuit,” “top-level circuit creation,” and “whole circuit design check of top-layer circuit of semiconductor integrated circuit.”
In the design process, if trouble occurs in the last step “whole circuit design check of top-layer circuit of semiconductor integrated circuit,” the process returns to the first “function circuit creation” step and a correction is made. In the design process, there is a possibility that a large number of artificial mistakes may occur such as a mistake at the circuit creation time and a design data pass mistake to the next step caused by the fact that a plurality of designers manually work in each step.
Thus, in the design method of creating the top-layer circuit in the related art, a plurality of designers manually work in each design step and thus the time taken for the design step is prolonged and an artificial mistake also occurs frequently and therefore a great deal of time is wasted as manual return is repeated.
Some semiconductor integrated circuits for mobile communications include a mechanism for dividing power supplied to the semiconductor integrated circuit into two or more channels and supplying or shutting off the power as required to realize low power consumption. In this mechanism, a state occurs in which a semiconductor element to which power is supplied and a semiconductor element to which no power is supplied are mixed according to the power supply and power shutoff combination of the two or more channels.
At this time, if a function circuit to which power is supplied receives output data of a function circuit to which no power is supplied as input, the input gate potential of the semiconductor element is not fixed and thus a leakage current flows.
To prevent a leakage current from flowing in design, it is necessary to create a power supply control signal and install a circuit for fixing the function circuit input potential in response to the power supply control specifications.
As an example of such a power supply control mechanism, a method of inputting a power supply control signal designed in response to the power supply control specifications to a function circuit as input signal and installing an AND gate for the input signal to the function circuit is available.
The design step of creating the power supply control circuit also tends to be divided among workers.
However, the design step is also conducted manually by a plurality of designers and thus the time taken for the design step is prolonged and an artificial mistake also occurs frequently and therefore a great deal of time is wasted as manual return is repeated.
In function verification of a semiconductor integrated circuit, function verification is conducted in response to the function to be checked. To conduct function verification, input data dynamically changing with input of a semiconductor integrated circuit (real values of high level, low level, intermediate potential, undefined value, etc.,) is input using a function verification tool and each function circuit is operated and the result is output. A comparison is made between the output result and the expectation value data previously describing the operation expected as the semiconductor integrated circuit specifications, whereby whether the function circuit operates normally or malfunctions can be checked.
The designer selects execution of function verification for each function circuit or in the one-chip circuit containing all function circuits considering the work efficiency in response to the check items of the function verification. In the one-chip circuit function verification of a large-scaled semiconductor integrated circuit, the handled data amount tends to become very large.
Particularly, in the one-chip circuit function verification, the used input data and expectation value data increase depending on the product of the number of terminals and the number of modes of the semiconductor integrated circuit and therefore the creation work of the input data and the expectation value data requires a great deal of time.
The input data and the expectation value data used for the function verification tend to be created manually by a plurality of designers.
Since the design steps involved in the function verification are also conducted manually by a plurality of designers, the time taken for the design steps is prolonged and an artificial mistake also occurs frequently and therefore a great deal of time is wasted as manual return is repeated.
As a related art for shortening the circuit design time period, Japanese Patent No. 2927137 discloses a design automation art of storing data defining the external specifications about already designed function circuits and put into parts and inputting the external specifications of the circuit to be designed and the circuit configuration, thereby reusing the already designed function circuits.
According to the art, after function circuit design completion, the function circuit and the input/output test specifications of the function circuit are given as input data and a test circuit is installed in the function circuit for conversion of the function circuit to the function circuit to which the test specifications are added, whereby the “test circuit installation in function circuit” step can be speeded up.
According to the art, however, only the “test circuit installation in function circuit” step is speeded up in the step sequence of creating the top-layer circuit and occurrence of waste of a great deal of time as manual return is repeated is not circumvented and therefore it is impossible to drastically reduce the number of design steps of a semiconductor integrated circuit.
To create the top-layer circuit rapidly and with no mistake, it is necessary to radically remedy “existence of a large number of design steps to create the top-layer circuit” and “manual work of a plurality of designers as work in each step” of the design method problems in the related arts.
To create the power supply control circuit rapidly and with no mistake in the power supply control circuit installation step, it is also necessary to radically remedy “manual work of a plurality of designers” of the design method problem in the related art.
In the step of creating the input data and the expectation value data used for the function verification, it is also necessary to radically remedy “manual work of a plurality of designers” of the design method problem in the related art.